RISC-V (pronounced \risk- ve") is a new instruction set architecture (ISA) that was originally9JD快充网络
designed to support computer architecture research and education, but which we now hope will
also become a standard free and open architecture for industry implementations. Our goals in
de ning RISC-V include:
• A completely open ISA that is freely available to academia and industry.
• A real ISA suitable for direct native hardware implementation, not just simulation or binary
translation.
• An ISA that avoids \over-architecting" for a particular microarchitecture style (e.g., microcoded,
in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom,
ASIC, FPGA), but which allows ecient implementation in any of these.
• An ISA separated into a small base integer ISA, usable by itself as a base for customized
accelerators or for educational purposes, and optional standard extensions, to support generalpurpose
software development.
• Support for the revised 2008 IEEE-754
oating-point standard [10].
• An ISA supporting extensive user-level ISA extensions and specialized variants.
• Both 32-bit and 64-bit address space variants for applications, operating system kernels, and
hardware implementations.
• An ISA with support for highly-parallel multicore or manycore implementations, including
heterogeneous multiprocessors.
• Optional variable-length instructions to both expand available instruction encoding space and
to support an optional dense instruction encoding for improved performance, static code size,
and energy eciency.
• A fully virtualizable ISA to ease hypervisor development.
• An ISA that simpli es experiments with new supervisor-level and hypervisor-level ISA designs.
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